1. Field of the Invention
The present invention relates to a semiconductor memory device having a ferroelectric capacitor and a method manufacturing the same.
2. Description of the Related Art
Recently, various memories have been developed; for example, a ferroelectric memory having ferroelectric capacitor and a dynamic random access memory (DRAM) having high dielectric capacitor are given as a semiconductor memory. In these ferroelectric memory and DRAM, the memory cell includes a selector transistor and a capacitor functioning as memory element connected to the selector transistor (e.g., JPN. PAT. APPLN KOKAI Publication No. 11-317500).
According to the conventional technique, after multi-layer interconnects of peripheral circuit and memory cell sections are formed, a capacitor of the memory cell section is formed. By doing so, the capacitor is formed at the uppermost layer. In this case, multi-layer interconnects are formed without being hindered by the capacitor, and also, capacitor degradation is prevented.
On the other hand, the multi-layer interconnects are formed after the capacitor is previously formed, and thereby, the capacitor is formed at the lower layer. In also case, the multi-layer interconnects are formed without being hindered by the capacitor, like the case described above, and there is no limitation of thermal process in forming the capacitor.
However, these advantages described above are obtained when the capacitor has two-dimensional structure, and is not so high. In this case, the capacitor having two-dimensional structure (hereinafter, referred to as two-dimensional capacitor) has the following structure. According to the structure, an electrode layer constituting the capacitor extends to only X and Y directions, that is, on the plane, and does not three-dimensionally extend to the Z direction.
In ferroelectric memory and DRAM, the technique of combining a three-dimensionally structural capacitor and multi-layer interconnects is required in order to realize high integration. In this case, the three-dimensionally structural capacitor (hereinafter, referred to as three-dimensional capacitor) has the following structure. According to the structure, an electrode layer constituting the capacitor does not only extend to X and Y directions, that is, on the plane, but also three-dimensionally extends to the Z direction.
However, if the structure according to the conventional technique is intactly applied to the three-dimensional capacitor, there is the following problem. More specifically, when the capacitor and multi-layer interconnects are formed in different layer, cell is enlarged because the three-dimensional capacitor has the height larger high than the two-dimensional capacitor.